DWN Accelerator on FPGA — Design-Space Study
Sweeping LUT-only neural networks across 40+ Artix-7 implementations to find where accuracy stops paying for area, and validating the winning design on every sample in the dataset.
- Period
- Summer 2026
- Role
- Solo
- Stack
- Verilog · Vivado · Python · Artix-7 · Basys 3
- Source
- Repository
- 102 MHz
- Artix-7, no DSPs or BRAM
- 12.7K
- LUTs
- 166K
- JSC samples validated on FPGA
- 30–40%
- LUT savings for 0.1% accuracy loss
The question
A Differentiable Weightless Neural Network computes by lookup rather than by multiplication, so it maps onto FPGA fabric directly — no DSPs, no BRAM, just logic. That’s the claim.
Building one implementation doesn’t test the claim, it demonstrates a single point. The question worth answering is the shape of the trade: as you shrink the network, how much area do you actually recover, and what does it cost in accuracy? A designer choosing this approach needs the curve, not an anecdote.
Getting the curve means dozens of implementations, each generated, verified, synthesized, and placed. By hand that’s not a study, it’s a semester.
Approach
The sweep is driven by dwn2rtl — the checkpoint-to-Verilog tool built for exactly this — which removed the manual step between a trained model and an implementable design. That made 40+ checkpoint-to-RTL Vivado implementations practical to run end to end.
The final design lands at 102 MHz on an Artix-7 in 12.7K LUTs, with zero DSPs and zero BRAM — the structural claim confirmed at the implementation level rather than asserted from the model’s math.
Verification
Two stages, cheapest first:
- 1,000 vectors, bit-exact. Generated RTL checked against the software model on a mix of reference and randomized inputs before any hardware was involved. The randomized portion matters: reference vectors tend to exercise the paths whoever wrote them was already thinking about.
- All 166,000 JSC samples on hardware. Not a sampled subset — every sample in the dataset, on the physical board.
Full-dataset validation is the claim I’d stand behind hardest. Simulation establishes that the logic is right; it doesn’t establish that the deployed bitstream, at the real clock, agrees with the model on every input the model will ever see. At 166K samples that stops being a statistical argument.
Results
| Finding | Value |
|---|---|
| LUT savings available | 30–40% |
| Accuracy cost | 0.1% |
| Implementations swept | 40+ |
| Final design | 102 MHz, 12.7K LUTs |
| DSPs / BRAM | 0 / 0 |
| Hardware validation | 166K / 166K samples |
Thirty to forty percent of the area for a tenth of a percent of accuracy is the useful output. It’s easy to assert that kind of trade and hard to establish it — this one comes from a swept space rather than a comparison between two hand-picked configurations, which is the difference between a finding and a coincidence.
What I’d do next
- Coverage on the generated testbenches. They check that outputs match; they don’t report which structural paths a given vector set exercised.
- Push past 102 MHz. The design closes comfortably. I never went looking for the ceiling.
- A second dataset. The area/accuracy curve is characterized on JSC. Whether its shape generalizes is an open question, not a settled one.